1. Field of the Invention
The present invention relates to a current sense amplifier capable of being operated in a stable manner at a low power voltage.
2. Description of the Related Art
In general, a current sense amplifier has an advantage over a voltage sense amplifier, since it operates at a higher speed, as compared to the voltage sense amplifier. Thus, the current sense amplifier can sense and amplify even small amounts of current. Accordingly, current sense amplifiers are often used in high-speed semiconductor devices. However, a common problem with the current sense amplifier is that it typically malfunctions at low power voltages (e.g., lower than power supply voltages used for normal operations).
FIG. 1 illustrates a circuit diagram of a conventional current sense amplifier As shown in FIG. 1, the conventional current sense amplifier contains a first PMOS input transistor P1 and a second PMOS input transistor P2. Each PMOS input transistor P1 and P2 has a source connected to an input signal line of a pair of input signal lines INL, INLB, a gate and a drain cross-coupled to the drain and the gate of the other PMOS transistor P1 or P2, respectively. References INL and INLB designate an input signal line and a complementary input signal line, respectively. The drains of the first and second PMOS transistors P1 and P2 are connected to first and second nodes n1 and n2, where an output signal CSA and a complementary output signal CSAB are respectively output.
The conventional sense amplifier further includes a first NMOS transistor N1 and a second NMOS transistor N2, each with a drain connected to the first node n1 and the second node n2, respectively, each with a gate coupled to its own drain, and each NMOS transistor having a source coupled to a common node n3. The current sense amplifier further includes a third NMOS transistor N3 with a drain connected to the common node n3, a gate receiving an enabling signal EN and a source connected to a ground voltage.
Operation of the conventional sense amplifier shown in FIG. 1 is described below. In operation, the conventional sense amplifier assumes that current i1 of the input signal line INL is slightly greater than current i2 of the complementary input signal line INLB. When an enabling signal (EN) with logic “high” level is applied to the gate of the third NMOS transistor N3, the third NMOS transistor N3 is turned on and the common node n3 becomes the ground voltage.
When voltage differences between the common node n3 and the first node n1, and between the common node n3 and the second node n2, are greater than threshold voltages of the first and second NMOS transistors N1, N2, respectively, and when voltage differences between the input signal line INL and the first node n1 and between the complementary input signal line INLB and the second node n2 are greater than threshold voltages of the first and second PMOS transistors P1, P2, respectively, the PMOS transistors P1 and P2 are turned on. Accordingly, the currents i1, i2 flow to NMOS transistors N1 and N2 via PMOS transistors P1 and P2, respectively.
At this time, voltage at the first node n1 is greater than voltage at the second node n2, because the current i1 of the input signal line INL is greater than the current i2 of the complementary input signal line INLB, and since resistance of the NMOS transistors N1 and N2 are the same. Therefore, resistance of the second PMOS transistor P2 becomes greater than resistance of the first PMOS transistor P1. As a result, a voltage difference between the first node n1 and second node n2 occurs. That is, voltage of the second node n2 is greater than voltage of the first node n1. However, this voltage difference value is small.
Operation of the circuit in FIG. 1 in which the current i1 is less than the current i2 is now described. When the enable signal (EN) having a “high” logic level is applied to the gate of the third NMOS transistor N3, the common node n3 becomes the ground voltage. Then, if voltage differences between the common node n3 and each of the first and the second nodes n1, n2, respectively, are greater than threshold voltages of the first and second NMOS transistors N1, N2, respectively, and if voltage differences between the input signal line INL and the first node n1 and between the complementary input signal line INLB and the second node n2 are greater than threshold voltages of the first and second PMOS transistors P1, P2, respectively, the PMOS transistors P1 and P2 are turned on. Accordingly, currents i1, i2 flow to the NMOS transistors N1 and N2 via PMOS transistors P1 and P2, respectively.
At this time, voltage at the first node n1 is less than voltage at the second node n2 because the current i1 on the input signal line INL is less than the current i2 on the complementary input signal line INLB, and resistance of the NMOS transistors N1 and N2 are the same. Therefore, resistance of the first PMOS transistor P1 becomes greater than resistance of the second PMOS transistor P2. As a result, a voltage difference between the first node n1 and the second node n2 occurs. That is, voltage of the second node n2 is greater than the first node n1. However, this voltage difference value is also small.
The conventional current sense amplifier circuit of FIG. 1 senses small amounts of current on the pair of the input signal lines INL, INLB, and generates a pair of output signals CSA, CSAB, each having a different voltage level. The current sense amplifier in FIG. 1 may be operated normally if the voltage of each of the input signal lines INL and INLB is greater than a total threshold voltage of the first PMOS transistor P1 and the second NMOS transistor N2, and greater than a total threshold voltage of the second PMOS transistor P2 and the first NMOS transistor N1. For example, if the threshold voltage of the PMOS transistors P1, P2 and the NMOS transistors N1, N2 is 0.8 V, respectively, the current sense amplifier in FIG. 1 may be normally operated when the voltage level of the input signal lines INL, INLB is greater than 1.6 V. In other words, if the voltage level of the input signal lines INL, INLB is less than 1.6 V, the current sense amplifier in FIG. 1 may not operate normally.
Therefore, the current sense amplifier of FIG. 1 may not be utilized for a semiconductor memory device that operates at a low power supply voltage (e.g., less than 1.6 V, for example). As the power supply voltage decreases to below 1.6 V, voltages of the input signal lines INL, INLB also decrease. However, threshold voltages of the PMOS and NMOS transistors should also decrease, for the current sense amplifier of FIG. 1 to be operated normally In practice, however, it is difficult to reduce the threshold voltage of the transistors.